1. Field of the Invention
The present invention relates to a controllable delay line.
2. Description of Related Art
Delay lines can be used in many applications, such as in phase-locked loops, delay-locked loops or time interval measuring. In addition, delay lines can be used in jitter measuring of PLL or DLL as well.
Controllable delay lines in the conventional design, however, are vulnerable by power voltage variation and have higher design cost, limited operation speed and limited maximum delay.
Based on the above-mentioned situation, such a controllable delay line is preferred that any influence caused by power voltage variation would be reduced and the operation speed and the maximum delay thereof would be increased.